发明名称 Mixed memory type hybrid cache
摘要 A hybrid cache includes a static random access memory (SRAM) portion and a resistive random access memory portion. Cache lines of the hybrid cache are configured to include both SRAM macros and resistive random access memory macros. The hybrid cache is configured so that the SRAM macros are accessed before the resistive random memory macros in each cache access cycle. While SRAM macros are accessed, the slower resistive random access memory reach a data access ready state.
申请公布号 US9304913(B2) 申请公布日期 2016.04.05
申请号 US201313843190 申请日期 2013.03.15
申请人 QUALCOMM INCORPORATED 发明人 Dong Xiangyu;Suh Jungwon
分类号 G06F12/00;G06F12/08;G11C11/16;G11C11/00;G11C13/00 主分类号 G06F12/00
代理机构 Seyfarth Shaw LLP 代理人 Seyfarth Shaw LLP
主权项 1. A hybrid cache apparatus, comprising: a first type of memory; a second type of memory; a first memory bank including the first type of memory and the second type of memory; and a first cache line including a first memory location in the first type of memory and a second memory location in the second type of memory within the first memory bank, the first cache line configured for accessing the first memory location before accessing the second memory location within the first memory bank during a cache accessing operation.
地址 San Diego CA US