Memory controller and data management method thereof

摘要

The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks.;In accordance with this configuration, upon performing a merge operation, hot pages and cold pages are determined, and the hot pages are respectively distributed to empty blocks, so that concentration of an erase operation on a specific physical block may be avoided, thus wear-leveling may be performed more efficiently.

主权项

1. A memory controller for managing correspondence between logical addresses and physical addresses of memory including a plurality of blocks, each having a plurality of pages, comprising:
a processor configured to:
classify pages in each block into hot pages and cold pages based on a predetermined criterion;select a first block to be merged which includes a first hot page and a second hot page;select at least one second block to be merged which does not include a hot page; andmerge the first block and the at least one second block by:
arranging the first hot page in a first target block,arranging the second hot page in a second target block,arranging a first part of pages in the at least one second block in the first target block, andarranging a second part of the pages in the least one second block in the second target block.