发明名称 |
System and method for multicore processing |
摘要 |
A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval. |
申请公布号 |
US9304880(B2) |
申请公布日期 |
2016.04.05 |
申请号 |
US201313843090 |
申请日期 |
2013.03.15 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Olivarez Michael L.;Benzel Stephen J.;Ehrlich Robert N.;McGowan Robert A. |
分类号 |
G06F11/00;G06F11/22 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising:
synchronizing debug signals from a plurality of processor cores to a common timing domain; transmitting debug messages based on the debug signals via a single debug interface common to all processor cores of the plurality of processor cores to enable tracking of processing completed within the plurality of processor cores during a common timing interval. |
地址 |
Austin TX US |