Baud rate phase detector with no error latches

摘要

Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and the comparison of the at least two consecutive data bits within the N consecutive data bits.

主权项

1. A phase detector, comprising:
a signal processor configured to separate an input signal into N consecutive data bits; a comparator configured to compare at least two consecutive data bits within the N consecutive data bits; a set of N estimation modules each configured to estimate a data bit value for each of the N consecutive data bits; and a computing module configured to determine a phase difference based on a data bit pattern formed by the data bit values of the N consecutive data bits and said comparison of the at least two consecutive data bits within the N consecutive data bits.