Magnetic random access memory and method of manufacturing the same

摘要

According to one embodiment, a memory includes a semiconductor layer including a trench which extends in a first direction, the trench having a first portion with a first depth and a second portion with a second depth deeper than the first depth, a gate insulating layer covering the semiconductor layer in the first portion, an element isolation layer covering the semiconductor layer in the second portion, the element isolation layer extending in a second direction from the second portion, a gate electrode provided on the gate insulating layer in the first portion and the element isolation layer in the second portion, the gate electrode filling the trench, and a third impurity region provided in the semiconductor layer directly below the second portion, the third impurity region being continuous in the first direction.

主权项

1. A magnetic random access memory comprising:
a semiconductor layer with a first conductivity type including a trench which extends in a first direction, the trench having a first portion with a first depth and a second portion with a second depth deeper than the first depth; a gate insulating layer covering the semiconductor layer in the first portion; an element isolation layer covering the semiconductor layer in the second portion, the element isolation layer extending in a second direction from the second portion, wherein the second direction is in parallel with an upper surface of the semiconductor layer, and the first and second directions intersect with one another; a gate electrode provided on the gate insulating layer in the first portion and the element isolation layer in the second portion, the gate electrode filling the trench; first and second impurity regions with a second conductivity type provided in the semiconductor layer, the first and second impurity regions sandwiching the gate electrode; a magnetoresistive element connected to the first impurity region; a first bit line connected to the magnetoresistive element; a second bit line connected to the second impurity region; and a third impurity region with the first conductivity type provided in the semiconductor layer directly below the second portion, wherein the third impurity region is continuous in the first direction, and the third impurity region has an impurity concentration higher than an impurity concentration of the semiconductor layer.