发明名称 |
Solving MLC NAND paired page program using reduced spatial redundancy |
摘要 |
Reduced spatial redundancy of lower bits data provides data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory assists in restoring the data, using less than a full back up storage. |
申请公布号 |
US9305655(B2) |
申请公布日期 |
2016.04.05 |
申请号 |
US201314038749 |
申请日期 |
2013.09.27 |
申请人 |
Virtium Technology, Inc. |
发明人 |
Phan Lan Dinh |
分类号 |
G11C14/00;G06F3/00;G11C16/22;G06F3/06;G11C11/56;G11C29/00 |
主分类号 |
G11C14/00 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method of managing a memory, the method comprising
configuring a first memory and a second memory,
wherein the first memory and the second memory each comprises a plurality of multi-level cell (MLC) memory cells,wherein each MLC memory cell comprises at least a least significant bit (LSB) and a most significant bit (MSB); copying first data from the first memory to the second memory,
wherein the first data comprise multiple LSB data and exclude all of the MSB data of the MLC memory cells of the first memory,wherein a first portion of the first data is copied to one or more LSBs of the MLC memory cells of the second memory,wherein a second portion of the first data is copied to one or more MSBs of the MLC memory cells of the second memory; writing second data to at least a MSB of the MLC memory cells of the first memory after copying the first data. |
地址 |
Rancho Santa Margarita CA US |