Circuit arrangement of gate side fan out area

摘要

The present invention is related to a circuit arrangement of a gate side fan out area. The circuit arrangement comprises: a first circuit module (T1), which the gate is coupled to a first input end (A), the drain and the source are respectively coupled to a second input end (B) and a Nth gate scan line (N); a first end (1) of the first circuit module is coupled to the first input end, a second end (2) is coupled to the second input end, and a third end (3) is coupled to the N+1th gate scan line (N+1); a first end (1) and a second end (2) of the second circuit module are coupled to the second input end (B), and a third end (3) is coupled to the Nth gate scan line (N); a first end (1) and a second end (2) of the third circuit module are coupled to the second input end (B), and a third end (3) is coupled to the N+1th gate scan line (N+1); a periodic square wave is inputted to the first input end (A), and a gate scanning signal is inputted to the second input end (B). The present invention is capable of enormously reducing the cost of a G-COF.

主权项

1. A circuit arrangement of a gate side fan out area, comprising: a first circuit module, a second circuit module, a third circuit module and a first transistor;
a gate of the first transistor is coupled to a first input end, a drain and a source of the first transistor are respectively coupled to a second input end and a Nth gate scan line, and N is a nature number; a first end of the first circuit module is coupled to the first input end, a second end of the first circuit module is coupled to the second input end, and a third end of the first circuit module is coupled to the N+1th gate scan line; a first end and a second end of the second circuit module are coupled to the second input end, and a third end of the second circuit module is coupled to the Nth gate scan line; a first end and a second end of the third circuit module are coupled to the second input end, and a third end of the third circuit module is coupled to the N+1th gate scan line; a periodic square wave is inputted to the first input end, and a gate scanning signal is inputted to the second input end, and a period of the periodic square wave is twice a scanning period of the gate scanning signal; the first circuit module is in off state between the second end and the third end when an input voltage to the first end of the first circuit module is equal to a first amplitude voltage of the periodic square wave; the first circuit module is in on state between the second end and the third end when an input voltage to the second end of the first circuit module is equal to a second amplitude voltage of the periodic square wave; the second circuit module is in off state between the second end and the third end when an input voltage to the first end of the second circuit module is equal to a first amplitude voltage of the periodic square wave; the second circuit module is in on state between the second end and the third end when an input voltage to the second end of the second circuit module is equal to a second amplitude voltage of the periodic square wave; the third circuit module is in off state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a first amplitude voltage of the periodic square wave; the third circuit module is in on state between the second end and the third end when an input voltage to the first end of the third circuit module is equal to a second amplitude voltage of the periodic square wave.