发明名称 Logical memory architecture, in particular for MRAM, PCRAM, or RRAM
摘要 An architecture and method are provided for reading and writing, in parallel or in series, an electronic memory component based on a two-dimensional matrix of two-terminal binary memory unit cells built into a crossbar architecture. The component includes a logical column-selector located outside the matrix and activating at least one column, one or more cells of which are subjected to read or write processing. Also provided is a component and method with the reading of the status of the cells by differential detection on from two cells of two different rows, either between a storage column and a constant reference column, or between two rows or two storage columns. A component is also provided in which specific selection structure is exclusively dedicated to read operations, and/or in which complementary cells in two complementary columns connected together are encoded in a single atomic operation by means of a single write current.
申请公布号 US9305607(B2) 申请公布日期 2016.04.05
申请号 US201214007017 申请日期 2012.03.23
申请人 UNIVERSITE PARIS SUD 11;CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE 发明人 Zhao Weisheng;Chaudhuri Sumanta;Chappert Claude;Klein Jacques-Olivier
分类号 G11C11/00;G11C5/06;G11C11/16;G11C13/00 主分类号 G11C11/00
代理机构 Greer, Burns & Crain, Ltd. 代理人 Greer, Burns & Crain, Ltd.
主权项 1. An electronic memory component, comprising: at least one two-dimensional matrix including a plurality of unitary memory cells, each of said unitary memory cells including two terminals, said unitary memory cells are each realized at the intersection of a first conductor defining a column and a second conductor defining a row within said matrix, and are each connected to said first and second conductors; and column selection means outside said matrix, said column selection means arranged according to a binary logic to selectively activate at least one column conductor connected to at least one defined cell that must be subjected to read or write processing, the column selection means including at least two transistors for each column, which are each arranged to connect at least said column conductor selectively to a first potential or to a second potential different from said first potential, wherein the connection of said column conductor to said first potential cooperates with read management means or write management means of at least one defined row to pass a read current, or a write current to one state in one direction, through a cell belonging to said column and to said row, and wherein the connection of said column conductor to said second potential cooperates with write management means of said at least one row in order to pass a write current to the other state through said cell in the other direction.
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