Integrated circuit design timing path verification tool

摘要

An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.

主权项

1. An electronic design automation (EDA) tool for validating a plurality of predefined timing paths of an integrated circuit design, wherein each timing path includes a plurality of digital logic elements, and wherein for the plurality of predefined timing paths there is a corresponding plurality of timing constraints, the EDA tool comprising:
a memory that stores the integrated circuit design; and a processor in communication with the memory, wherein the processor includes:
means for receiving a first set of timing constraints corresponding to a first multi-cycle timing path of the plurality of predefined timing paths, wherein the first multi-cycle timing path includes a first set of digital logic elements and requires a first number of clock cycles for a signal to propagate there-across;means for validating the first multi-cycle timing path and the first set of timing constraints by performing a unit-delay, gate-level netlist simulation of the first multi-cycle timing path;means for performing a static-timing-analysis (STA) of the integrated circuit design and generating a STA timing report that includes the first set of timing constraints and instances of the first set of digital logic elements;means for generating a simulation-based checker based on the STA timing report and integrating the simulation-based checker with the unit-delay, gate-level netlist simulation;means for determining that the first multi-cycle timing path requires a second number of clock cycles for the signal to propagate there-across, wherein the first and second numbers of clock cycles correspond to clock cycles of an external clock signal used to simulate the integrated circuit design,wherein the simulation-based checker validates the first multi-cycle timing path by counting a number of clock cycles of the external clock signal required for the signal to propagate across the first multi-cycle timing path and invalidates the first multi-cycle timing path when the first multi-cycle timing path requires the second number of clock cycles for the signal to propagate across the first multi-cycle timing path during the unit-delay, gate-level netlist simulation,wherein the simulation-based checker generates an interrupt report when the signal stops propagating across the first multi-cycle timing path, and wherein the interrupt report indicates a position of a digital logic element of the first set of digital logic elements to which the first multi-cycle timing path is exercised;means for redefining the first multi-cycle timing path to take the second number of clock cycles for the signal to propagate there-across by modifying the first set of timing constraints; andmeans for generating a simulation log file upon completing the unit-delay, gate-level netlist simulation, and wherein the simulation log file includes a PASS status message when the first multi-cycle timing path is successfully validated by the simulation-based checker, and a FAIL status message when the first multi-cycle timing path is invalidated by the simulation-based checker, during the unit-delay, gate-level netlist simulation.