发明名称 Junction field-effect floating gate memory switch with thin tunnel insulator
摘要 A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.
申请公布号 US9305650(B2) 申请公布日期 2016.04.05
申请号 US201414181427 申请日期 2014.02.14
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Gopalakrishnan Kailash;Hekmatshoartabari Bahman
分类号 G11C11/34;G11C16/10;H01L29/78;H01L27/12;H01L29/66;H01L21/28;H01L29/423;H01L29/788;G11C16/04 主分类号 G11C11/34
代理机构 Otterstedt, Ellenbogen & Kammer, LLP 代理人 Percello Louis J.;Otterstedt, Ellenbogen & Kammer, LLP
主权项 1. A field-effect floating gate memory device comprising: a channel region having a conductivity type and adjoining an electrically insulating substrate; doped source and drain regions operatively associated with and having the same conductivity type as the channel region; a control gate; a floating gate for storing carriers from the channel region, the floating gate being positioned between the channel region and the control gate, the floating gate having a doping type opposite to the conductivity type of the channel region; a first, high-k dielectric layer thinner than five nanometers between the channel region and the floating gate and positioned to facilitate the direct tunneling of majority carriers from the channel region into the floating gate, the first, high-k dielectric layer being configured to provide a lower barrier for the tunneling of majority carriers from the channel region into the floating gate compared to that for minority carriers in the channel region, and a second dielectric layer between the control gate and the floating gate, wherein the channel region is comprised of n-type silicon, the first, high-k dielectric layer having at least one of a lower conduction band-offset with the channel region than its valence band-offset with the channel region and a lower effective mass for electrons than holes.
地址 Armonk NY US