Implementing ECC control for enhanced endurance and data retention of flash memories

摘要

A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.

主权项

1. A method for implementing ECC (Error Correction Codes) control in a flash memory system comprising:
providing a flash test and maintenance engine (FTME) coupled to each flash chip in the flash memory system; monitoring in a background process a VT (threshold voltage) to determine VT degradation of cells and blocks in a flash memory with the FTME used to measure and process VT measurement and determine VT degradation of the of cells and blocks in each flash chip in the flash memory system; providing a first ECC engine having a first level of ECC capability; providing a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer delay than the first ECC engine; responsive to receiving a read request to a particular cell/block, comparing the determined VT degradation with a threshold, and using the first ECC engine if the determined VT degradation is less than the threshold and using the second ECC engine if the determined VT degradation is above the threshold.