Network interface circuitry with flexible memory addressing capabilities

摘要

An integrated circuit that includes network interface circuitry is provided. The network interface circuitry may include memory for buffering incoming data and associated control circuitry for loading the incoming data into and retrieving data from memory. The memory may be organized into multiple individually addressable memory blocks. The control circuitry may include read and write barrel shifters, a controller for providing read and write address signals, write address circuitry for controlling the write barrel shifter and for generating write address bits, and read address circuitry for controlling the read barrel shifter and for generating read address bits. The read and write circuitry may each include division and modulus arithmetic circuits for processing the address signals received from the controller and may include control logic for generating the read and write address bits that are used to address each of the multiple memory blocks.

主权项

1. A method of operating an integrated circuit having memory that includes a plurality of memory blocks, comprising:
receiving data; reordering the received data using at least first and second serially connected shifter circuit stages, wherein the first shifter circuit stage receives a first set of data words, wherein the second shifter circuit stage receives a second set of data words, wherein the first shifter circuit stage selectively rotates the first set of data words by a first number of words, and wherein the second shifter circuit stage selectively rotates the second set of data words by a second number of words that is different from the first number of words; loading a first portion of the reordered data into a first row of each memory block in a first subset of memory blocks in the plurality of memory blocks; loading a second portion of the reordered data into a second row of each memory block in a second subset of memory blocks in the plurality of memory blocks, wherein the second row is adjacent to the first row, and wherein the first and second portions of the reordered data are simultaneously loaded into the memory; and outputting the data from the memory.