发明名称 Nonvolatile semiconductor memory device
摘要 A nonvolatile semiconductor memory device includes a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein and a control circuit that performs a writing operation on the memory cells. The writing operation performed by the control circuit includes a pre-programming verification operation to determine a threshold level of a memory cell in an erasure state, and a program operation in which a program voltage is selected from a plurality of program voltages on the basis of a determination result of the pre-programming verification operation.
申请公布号 US9305637(B2) 申请公布日期 2016.04.05
申请号 US201414194781 申请日期 2014.03.02
申请人 Kabushiki Kaisha Toshiba 发明人 Funatsuki Rieko;Futatsuyama Takuya;Arai Fumitaka
分类号 G11C11/34;G11C11/56;G11C16/04;G11C16/34 主分类号 G11C11/34
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A nonvolatile semiconductor memory device comprising: a memory cell array having nonvolatile memory cells in which one of multiple values is programmable therein by setting one of a plurality of threshold values therein; and a control circuit configured to perform a writing operation on the memory cells of the memory cell array, wherein the writing operation performed on a memory cell in an erasure state includes a pre-programming verification operation to determine a threshold level of the memory cell in the erasure state and a program operation in which a program voltage for the memory cell is selected from a plurality of program voltages based on a determination result of the pre-programming verification operation, wherein the control circuit selects and writes a first program voltage to a memory cell which is determined to have a threshold level larger than a reference value in the pre-programming verification operation, and selects and writes a second program voltage lower than the first program voltage to a memory cell which is determined to have a threshold level smaller than the reference value in the pre-programming verification operation.
地址 Tokyo JP