发明名称 Shift register unit, gate driving circuit and display apparatus
摘要 The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit and a display apparatus, the shift register unit includes an inputting module, a first outputting module and a second outputting module. As compared with the prior art, the structure of the shift register unit can be simplified effectively, and the number of use of the transistors can be further reduced. Embodiments of the present disclosure are used to implement scanning and driving.
申请公布号 US9305509(B2) 申请公布日期 2016.04.05
申请号 US201314368403 申请日期 2013.11.11
申请人 BOE TECHNOLOGY GROUP CO., LTD.;ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. 发明人 Li Fuqiang;Li Cheng;An Seong Jun
分类号 G09G3/36;G09G3/00;G11C19/28 主分类号 G09G3/36
代理机构 Ladas & Parry LLP 代理人 Ladas & Parry LLP
主权项 1. A shift register unit comprising: an inputting module connected with a first signal input terminal, a second signal input terminal, a first voltage terminal, a second voltage terminal and a first outputting module, and configured to control a scan direction of the shift register unit according to a signal inputted from the first signal input terminal, a signal inputted from the second signal input terminal, a voltage inputted from the first voltage terminal and a voltage inputted from the second voltage terminal; the first outputting module connected with a first clock signal terminal, a first node and a first signal output terminal, and configured to control a potential of a signal outputted from the first signal output terminal according to a signal outputted from the inputting module and a first clock signal inputted from the first clock signal terminal, the first node being a connection node of the first outputting module and a second outputting module; and the second outputting module connected with the first node, a second clock signal terminal and a second signal output terminal, and configured to control a potential of a signal outputted from the second signal output terminal according to a signal at the first node and a second clock signal inputted from the second clock signal terminal.
地址 Beijing CN