| 摘要 |
An encoder circuit comprises an encoder unit, which encodes the states of a plurality of delay signals by performing: a first operation that detects the positions where the logic states of two or more delay signals included in a signal group change from HIGH to LOW, said signal group being constituted by at least two of said delay signals latched by a latch unit, all of said delay signals included in the signal group being arranged in a sequence based on the sequence of connection of a plurality of delay units; a second operation that detects the positions where the logic states of two or more said delay signals included in the signal group change from LOW to HIGH; and a third operation that detects that the logic states of two or more said delay signals including at least one said delay signal included in the signal group are a predetermined state, said third operation being different from said first operation and from said second operation. |
