INTEGRATED CIRCUIT WTH LOW POWER SCAN FLIP-FLOP

摘要

A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.

主权项

1. An integrated circuit, comprising:
a first flip-flop including:
a first multiplexer having a first input terminal for receiving a first data input signal, a second input terminal for receiving a scan data input signal, a select input terminal for receiving a scan enable signal, and an output terminal for outputting at least one of the first data input and scan data input signals based on the scan enable signal;a first latch having an input terminal connected to the output terminal of the first multiplexer for receiving at least one of the first data input and scan data input signals, a clock input terminal for receiving an inverted clock signal, and an output terminal for outputting an intermediate first output signal; anda second latch having an input terminal connected to the output terminal of the first latch for receiving the intermediate first output signal, a clock input terminal for receiving a clock signal, and an output terminal for outputting a first output signal; and a second flip-flop including:
a second multiplexer having a first input terminal for receiving a second data input signal, a second input terminal connected to the output terminal of the second latch for receiving the first output signal, a select input terminal for receiving the scan enable signal, and an output terminal for outputting at least one of the second data input and first output signals based on the scan enable signal;a first logic circuit for generating a first intermediate clock signal at an output terminal thereof based on the clock signal, the scan data input signal, the first output signal, and the scan enable signal;a third latch having an input terminal connected to the output terminal of the second multiplexer for receiving at least one of the second data input and first output signals, a clock input terminal connected to the output terminal of the first logic circuit for receiving the first intermediate clock signal, and an output terminal for outputting an intermediate second output signal based on the first intermediate clock signal; anda fourth latch having an input terminal connected to the output terminal of the third latch for receiving the intermediate second output signal, a clock input terminal for receiving the clock signal, and an output terminal for outputting a second output signal, wherein the fourth latch outputs the second output signal based on the intermediate second output signal.