发明名称 |
BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS |
摘要 |
A method in a processor includes receiving an instruction indicating a first source packed data operand having a first plurality of data elements each having a plurality of bit groups, and indicating a second source packed data operand having a second plurality of data elements each having a plurality of bit groups. Each data element of the first plurality corresponding to a different data element of the second plurality in a corresponding position. Each bit group in each data element of the first plurality corresponding to a different bit group in a corresponding position in a corresponding data element of the second plurality. Storing a result packed data operand in a destination storage location in response to the instruction. The result packed data operand including every other bit group of the first source packed data operand interleaved with every other corresponding bit group of the second source operand. |
申请公布号 |
WO2016048630(A1) |
申请公布日期 |
2016.03.31 |
申请号 |
WO2015US48623 |
申请日期 |
2015.09.04 |
申请人 |
INTEL CORPORATION |
发明人 |
ESPASA, ROGER;GUILLEN FANDOS, DAVID;SOLE, GUILLEM |
分类号 |
G06F9/30;G06F9/06 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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