发明名称 |
LATCH OFFSET CANCELATION SENSE AMPLIFIER |
摘要 |
Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the preamplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell. |
申请公布号 |
WO2016048739(A1) |
申请公布日期 |
2016.03.31 |
申请号 |
WO2015US50361 |
申请日期 |
2015.09.16 |
申请人 |
QUALCOMM INCORPORATED;INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY |
发明人 |
JUNG, SEONG-OOK;NA, TAEHUI;SONG, BYUNGKYU;KIM, JUNG PILL;KANG, SEUNG HYUK |
分类号 |
G11C11/16;G11C7/06;G11C7/08;G11C7/12 |
主分类号 |
G11C11/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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