VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE

摘要

Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

主权项

1. An apparatus comprising:
first and second full voltage level shifters configured to receiver self-clocked true and complement data input signals in a first voltage domain and generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain; and first and second complementary metal oxide semiconductor (CMOS) circuits configured to generate voltage level shifted self-clocked tristated true and complement output signals in the second voltage domain based on the voltage level shifted self-clocked intermediate true and complements signals.