Conditional Termination and Conditional Termination Predicate Instructions

摘要

In an embodiment, a processor may implement a vector instruction set including a conditional termination instruction (CTerm). The CTerm instruction may take two source operands and compare them according to a specified condition, updating flags as a result of the instruction. The flags may be used to affect predicate vector generation to control vectorized loop execution. In an embodiment, the vector instruction set may also include a conditional termination predicate instruction (CTPred). The CTPred instruction may take a pair of predicate vectors and a set of flags as operands, and may generate: a predicate vector to control parallel processing of vector elements, and a set of flags to control further loop processing. Either instruction may be used to efficiently manage vector loops in various embodiments, or the instructions may be used together.

主权项

1. A processor comprising:
an execution core configured to execute a first vector instruction having a first operand and a second operand, wherein:
the execution core is configured to generate one or more result flags responsive to a comparison of the first operand and the second operand based on a comparison condition specified by the first vector instruction;the execution core is configured to pass at least a first flag of the one or more flags through unmodified in response a first outcome of the comparison condition; andthe execution core is configured to output the first flag in a predetermined state responsive to a second outcome of the comparison condition that is an opposite logical value to the first outcome.