| 摘要 |
A reconfigurable arithmetic device includes a plurality of processor elements configured to perform first arithmetic processes corresponding to a first type of instruction and second arithmetic processes corresponding to a second type of instruction, a random-access memory (RAM), and a control unit. The first type of instruction is written into the RAM at a first address, data for the first type of instruction is written into the RAM at a second address, and data for the second type of instruction is written into the RAM at a third address. When the first type of instruction is written at the first address, the control unit decodes the first type of instruction and configures the processor elements to perform the first arithmetic processes. When data for the second type of instruction is written at the third address, the control unit configures the processor elements to perform the second arithmetic processes. |
