发明名称 INSTRUCTION AND LOGIC FOR HARDWARE COMPRESSION WITH TILED DATA STRUCTURES OF DISSIMILAR DIMENSIONS
摘要 An apparatus includes a controller and a compression unit. The controller includes logic to receive an input line of data from a data producer and divide the input line of data into a plurality of segment. Each segment corresponds to a compression context and to a multi-line data tile. The controller also includes logic to write a first segment of the input line to a first multi-line data tile, and to write a second segment of the input line to a second multi-line data tile upon reaching a boundary of the first multi-line data tile. The compression unit includes logic to apply a first compression context to the first multi-line data tile and a second compression context to the second multi-line data tile.
申请公布号 US2016092112(A1) 申请公布日期 2016.03.31
申请号 US201414496300 申请日期 2014.09.25
申请人 Intel Corporation 发明人 Akgun Hasmet;Shivakumar Premkishore;Limaye Deepak
分类号 G06F3/06 主分类号 G06F3/06
代理机构 代理人
主权项 1. An apparatus, comprising: a controller including: a first logic to receive an input line of data from a data producer;a second logic to divide the input line of data into a plurality of segments, each segment corresponding to a compression context and to a multi-line data tile;a third logic to write a first segment of the input line to a first multi-line data tile; anda fourth logic to write a second segment of the input line to a second multi-line data tile upon reaching a boundary of the first multi-line data tile; and a compression unit including a fifth logic to apply a first compression context to the first multi-line data tile and a second compression context to the second multi-line data tile.
地址 Santa Clara CA US