| 发明名称 |
MEMORY DEVICE, MEMORY CELL AND MEMORY CELL LAYOUT |
| 摘要 |
A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate. |
| 申请公布号 |
US2016093628(A1) |
申请公布日期 |
2016.03.31 |
| 申请号 |
US201414500425 |
申请日期 |
2014.09.29 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHEN Shih-Hsien;KUO Liang-Tai;LU Hau-Yan;KO Chun-Yao |
| 分类号 |
H01L27/115;H01L49/02;H01L29/10;H01L27/02;H01L23/528;H01L29/788;H01L29/49 |
主分类号 |
H01L27/115 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory cell comprising:
a first transistor coupled to a source line; a second transistor coupled to the first transistor and a bit line; a first capacitor coupled to a word line and the second transistor; and a second capacitor coupled to the second transistor and an erase gate. |
| 地址 |
Hsinchu TW |
