CHECKPOINTS FOR A SIMULTANEOUS MULTITHREADING PROCESSOR

摘要

According to an aspect, a system for checkpoint acceleration in a simultaneous multithreading (SMT) processor includes circuitry of a processor core of the SMT processor to execute one or more threads in a processing pipeline. The processing pipeline includes a completion stage followed by a checkpoint stage. The system also includes a checkpoint accelerator disposed between the completion stage and the checkpoint stage. The checkpoint accelerator includes a backlog queue that stores a list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle. The checkpoint accelerator also includes a selection control that drives one or more of the next-to-complete groups of instructions from the backlog queue to the checkpoint stage based on one or more completion indicators that identify which of the next-to-complete groups of instructions actually completed.

主权项

1. A system for checkpoint acceleration in a simultaneous multithreading (SMT) processor, the system comprising:
circuitry of a processor core of the SMT processor to execute one or more threads comprising in a processing pipeline comprising a completion stage followed by a checkpoint stage; and a checkpoint accelerator disposed between the completion stage and the checkpoint stage, the checkpoint accelerator comprising a backlog queue that stores a list of next-to-complete groups of instructions from the one or more threads anticipated to complete in an upcoming cycle and a selection control that drives one or more of the next-to-complete groups of instructions from the backlog queue to the checkpoint stage based on one or more completion indicators that identify which of next-to-complete groups of instructions actually completed.