NAND MEMORY ADDRESSING

摘要

Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).

主权项

1. A memory controller operable to perform addressing in a NAND memory,
the memory controller having circuitry configured to:
identify a defined number of address cycles supported at either the memory controller or the NAND memory to address individual memory units in the NAND memory;select the defined number of address cycles in which to operate in order to address the individual memory units in the NAND memory; andconfigure either the memory controller or the NAND memory to operate at the selected number of address cycles.