INSTRUCTION AND LOGIC FOR ADAPTIVE DATASET PRIORITIES IN PROCESSOR CACHES

摘要

A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

主权项

1. A processor, comprising:
a front end including a first logic to receive an instruction defining a priority dataset, the priority dataset including a plurality of ranges of memory addresses, each range corresponding to a respective priority level; a cache; and a cache controller, including:
a second logic to detect a miss in the cache for a requested cache value;a third logic to determine a candidate cache victim from the cache;a fourth logic to determine a priority of the requested cache value according to the priority dataset;a fifth logic to determine a priority of the candidate cache victim according to the priority dataset; anda sixth logic to evict the candidate cache victim based on whether the priority of the candidate cache victim is less than or equal to the priority of the requested cache value.