| 摘要 |
PROBLEM TO BE SOLVED: To provide an error detection code generation circuit for faster arithmetic circuit.SOLUTION: An error detection code generation circuit has a plurality of first XOR generation circuits generating a first XOR bit for 12 bits assigned to a decimal number 3 digits, included in a decimal number data of first format representing the number from 0 to 9 by 4 bits, respectively, a second XOR generation circuit generating a second XOR bit for 4 bits assigned to a decimal number 1 digit, included in a decimal number data of first format, and a third XOR generation circuit generating a third XOR bit for the first XOR bit and second XOR bit and a code bit and an exponent bit, as an error detection XOR bit of a decimal number data of second format representing a decimal number 3 digits by 10 bits subjected to format conversion from the decimal number data of first format. The error detection code generation circuit outputs the error detection XOR bit and a modulo 3 of decimal number data of first format, as the error detection redundant data of decimal number data of second format.SELECTED DRAWING: Figure 14 |
