发明名称 |
LDPC DECODER WITH EFFICIENT CIRCULAR SHIFTERS |
摘要 |
A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix. |
申请公布号 |
US2016094245(A1) |
申请公布日期 |
2016.03.31 |
申请号 |
US201414499284 |
申请日期 |
2014.09.29 |
申请人 |
APPLE INC. |
发明人 |
Landau Asaf;Ish-Shalom Tomer;Tate Yonathan |
分类号 |
H03M13/11;H03M13/00 |
主分类号 |
H03M13/11 |
代理机构 |
|
代理人 |
|
主权项 |
1. A decoder, comprising:
variable-node circuitry and check-node circuitry, which are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that comprises L-by-L sub-matrices, wherein the variable-node circuitry and the check-node circuitry are further configured to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC; and a Message Passing (MP) module, which comprises multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1, and which is configured to schedule the variable-node circuitry and the check-node circuitry in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix. |
地址 |
Cupertino CA US |