GLITCH LESS DELAY CIRCUIT FOR REAL-TIME DELAY ADJUSTMENTS

摘要

An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.

主权项

1. An apparatus, comprising:
a first delay unit configured to:
delay propagation of a signal by a first delay time responsive to a first value of a first control signal; anddelay propagation of the signal by a second delay time responsive to a second value of the first control signal; a second delay unit configured to:
delay propagation of an output of the first delay unit by a third delay time responsive to a first value of a second control signal; anddelay propagation of the output of the first delay unit by a fourth delay time responsive to a second value of the second control signal; and circuitry configured to:
change the first control signal from the second value to the first value responsive to a determination that the output of the first delay unit and an output of the second delay unit are both a same logic value.