Two-Transistor SRAM Circuit and Methods of Fabrication

摘要

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

主权项

1. In an integrated circuit having at least one logic circuit operating within a MOSFET logic circuit range and a plurality of memory cells arranged in an array interconnected by a plurality of complementary bit line pairs and a plurality of word lines, each memory cell comprising:
a thyristor having an anode and a cathode connected to a bit line and a word line in a cross point arrangement; the thyristor having regions electrically biased so that voltage swings on the bit line and the word line, operating within the MOSFET logic circuit range, are sufficient to read and write the memory cell; and wherein the voltage to read and write the memory cells is higher than an upper voltage of the MOSFET logic circuit range.