发明名称 半導体素子搭載用パッケージ基板の製造方法
摘要 Disclosed is a method for manufacturing a package substrate for semiconductor element mounting, with which improvement in yield can be achieved by suppressing deposition of resin powder, the surface can be formed having circuitry constituting an external layer with respect to an insulating layer with said circuitry being very fine and providing excellent adhesive force due to the formation of embedded circuitry without undercutting, and various types of metal structures such as bumps and pillars can be formed by the formation of three-dimensional circuitry at arbitrary locations. The method for manufacturing a package substrate for semiconductor element mounting comprises: a step for preparing a multilayer metal foil in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated, and for forming a core substrate by laminating the multilayer metal foil on a substrate; a step for physically removing the first carrier metal foil of the multilayer metal foil; a step for performing first pattern plating on the second carrier metal foil; a step for forming a laminated body by laminating the insulating layer on the first pattern plating; a step for separating the laminated body together with the second carrier metal foil from the core substrate; and a step for performing etching by forming an etching resist on the second carrier metal foil of the laminated body that has been separated.
申请公布号 JP5896200(B2) 申请公布日期 2016.03.30
申请号 JP20110207249 申请日期 2011.09.22
申请人 日立化成株式会社 发明人 田村 匡史;杉林 学;鈴木 邦司;服部 清男
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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