发明名称 |
Bit shuffle processors, methods, systems, and instructions |
摘要 |
A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element. |
申请公布号 |
EP3001307(A1) |
申请公布日期 |
2016.03.30 |
申请号 |
EP20140382361 |
申请日期 |
2014.09.25 |
申请人 |
INTEL CORPORATION |
发明人 |
ESPASA, ROGER;SOLE, GUILLEM;GUILLEN FANDOS, DAVID |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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