发明名称 Method for driving liquid crystal display device
摘要 A liquid crystal material is prevented from being degraded by a voltage to control the shift of the threshold voltage which is applied to a back gate on the same conductive film as a pixel electrode. A liquid crystal display device includes a pixel circuit including a pixel electrode which applies an electric field to a liquid crystal layer; and a driver circuit including a transistor including a first gate and a second gate with a semiconductor film interposed therebetween. The transistor overlaps with the liquid crystal layer. A signal for controlling on/off of the transistor is input to the first gate. A signal for applying a first voltage is input to the second gate in a gate line selection period. A signal for alternately applying the first voltage and a second voltage is input to the second gate in a vertical retrace period.
申请公布号 US9299296(B2) 申请公布日期 2016.03.29
申请号 US201313949258 申请日期 2013.07.24
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yamazaki Shunpei;Koyama Jun
分类号 G09G5/00;G09G3/36;G11C19/28;G02F1/1368;H03K17/30 主分类号 G09G5/00
代理机构 Robinson Intellectual Property Law Office 代理人 Robinson Intellectual Property Law Office ;Robinson Eric J.
主权项 1. A method for driving a liquid crystal display device, the liquid crystal display device comprising: a driver circuit including a first transistor and a second transistor each comprising a first gate and a second gate with a semiconductor film between the first gate and the second gate, wherein the second gate of the first transistor and the second gate of the second transistor are back gates which are directly connected to each other, the method comprising the steps of: applying a first voltage to the second gate of the first transistor and the second gate of the second transistor in a gate line selection period; andalternately applying the first voltage and a second voltage to the second gate of the first transistor and the second gate of the second transistor in a vertical retrace period, wherein an input of a clock signal to the driver circuit is stopped in the vertical retrace period.
地址 Kanagawa-ken JP
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