发明名称 Memory system and constructing method of logical block
摘要 According to one embodiment, a memory system includes a bit-error-rate manager configured to manage information associated with a bit error rate for each physical block, a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, and a block manager configured to manage the correspondence between the logical block constructed by the logical-block constructing unit and the physical blocks. The logical block is a collection of a plurality of physical blocks.
申请公布号 US9298534(B2) 申请公布日期 2016.03.29
申请号 US201414193452 申请日期 2014.02.28
申请人 Kabushiki Kaisha Toshiba 发明人 Miyamoto Arata;Yao Hiroshi
分类号 H04L1/20;G06F11/07 主分类号 H04L1/20
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A memory system, comprising: a non-volatile memory that includes a plurality of memory chips, each of the memory chips including a plurality of physical blocks; and a controller configured to control the non-volatile memory, wherein the controller includes a bit-error-rate manager configured to manage information associated with a bit error rate for each of the physical blocks,a logical-block constructing unit configured to construct a logical block based on the information associated with the bit error rate, the logical block being a collection of the plurality of physical blocks, anda block manager configured to manage a correspondence between the logical block constructed by the logical-block constructing unit and the plurality of physical blocks.
地址 Minato-ku JP