Performing quotient selection for a carry-save division operation

摘要

The disclosed embodiments disclose techniques for performing quotient selection in an iterative carry-save division operation that divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D. During a divide operation, a divider approximates Q by iteratively selecting an operation to perform for each iteration of the carry-save division operation and then performing the selected operation. The operation for each iteration is selected based on the current partial sum bits of a partial remainder in carry-save form (rs) and the current partial carry bits of a partial remainder in carry-save form (rc). More specifically, the operation is selected from a set of operations that includes: (1) a 2X* operation; (2) an S1 & 2X* operation; (3) an S2 & 2X* operation; (4) an A1 & 2X* operation; and (5) an A2 & 2X* operation.

主权项

1. In an integrated circuit (IC), a method for performing quotient selection for a carry-save division operation, wherein the carry-save division operation divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D, the method comprising:
circuitry in the IC approximating Q by iteratively selecting and performing an operation for each iteration of the carry-save division operation, wherein the operation for a given iteration is selected based on a set of partial sum bits of a partial remainder in carry-save form (rs) and a set of partial carry bits of a partial remainder in carry-save form (rc); wherein the operation for the given iteration is selected from a set of operations that comprises:
a “2X* operation” in which an inverting shift circuit in the IC performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 0 is retired;an “S1 & 2X* operation” in which a carry-select addition circuit in the IC subtracts the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 1 is retired;an “S2 & 2X* operation” in which the carry-select addition circuit subtracts twice the divisor from rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit 2 is retired;an “A1 & 2X* operation” in which the carry-select addition circuit adds the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −1 is retired; andan “A2 & 2X* operation” in which the carry-select addition circuit adds twice the divisor to rs and rc, the inverting shift circuit performs a left shift of rs and rc and inverts the most-significant bit of rs and rc, and a quotient digit −2 is retired.