Fabrication method and structure of semiconductor non-volatile memory device

摘要

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

主权项

1. A manufacturing method of a semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor substrate, comprising the steps of:
(a) forming a first insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit region; (b) forming a first conductive film over the first insulating film of the memory cell region and the peripheral circuit region; (c) selectively patterning the first conductive film of the memory cell region while leaving the first conductive film of the peripheral circuit region, thereby forming a first gate electrode in the memory cell region; (d) forming a second insulating film including a charge storing region over the memory cell region and the peripheral circuit region after the step (c); (e) forming a second conductive film over the second insulating film of the memory cell region and the peripheral circuit region; (f) etching back the second conductive film, thereby removing the second conductive film in the peripheral circuit region and forming a second gate electrode via the second insulating film on a sidewall of the first gate electrode in the memory cell region; and (g) patterning the first conductive film of the peripheral circuit region, thereby forming a third gate electrode in the peripheral circuit region after the step (f).