| 摘要 |
According to one embodiment of the present invention, a layout verifying method, extracting the layout of a fin based integrated circuit in a layout design and verification system with a device code. The method includes the following steps: the layout design system receiving the layout of a specific integrated circuit unit; extracting device codes in units of gate lines by referring to the number of intersecting points of an active region of the layout, the gate lines, and silicon pins; and combining the device codes extracted in the order of each of the gate lines. |
