发明名称 Method of wafer dicing using hybrid laser scribing and plasma etch approach with mask plasma treatment for improved mask etch resistance
摘要 Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is exposed to a plasma treatment process to increase an etch resistance of the mask. The mask is patterned with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to exposing the mask to the plasma treatment process, the semiconductor wafer is plasma etched through the gaps in the mask to singulate the integrated circuits.
申请公布号 US9299611(B2) 申请公布日期 2016.03.29
申请号 US201414167300 申请日期 2014.01.29
申请人 Applied Materials, Inc. 发明人 Lei Wei-Sheng;Eaton Brad;Kumar Ajay;Papanu James S.;Park Jungrae
分类号 H01L31/06;H01L21/78;H01L21/308;H01L21/3065;H01L21/67;H01L21/027;H01L21/3105;H01L21/311 主分类号 H01L31/06
代理机构 Blakely Sokoloff Taylor Zafman LLP 代理人 Blakely Sokoloff Taylor Zafman LLP
主权项 1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising: forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; exposing the mask to a plasma treatment process to increase an etch resistance of the mask; patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits, wherein the exposing the mask to the plasma treatment process is performed prior to patterning the mask with the laser scribing process; and subsequent to exposing the mask to the plasma treatment process, plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits.
地址 Santa Clara CA US