Miniature wire-bondable capacitor

摘要

A multi-layer ceramic capacitor (MLCC) device includes a ceramic chip having electrically conductive layers embedded within the chip that form one or more capacitors connected by one or more vias to one or more upwardly facing wire-bondable pads on the top side of the device. One embodiment includes electrically conductive layers that form at least two stacked capacitors connected by vias to multiple upwardly facing wire-bondable pads on the top side, whereby the MLCC device has a reduced footprint while avoiding solder fillets. The wire-bondable pads may lie in a common plane or be pyramidally stepped. Metallization on the PCB-facing bottom side and at least one of the ends of the ceramic chip of another embodiment forms a downwardly facing capacitor terminal.

主权项

1. A multi-layer ceramic capacitor device, comprising:
a ceramic chip having a top side, a bottom side, a front side, a back side, a left end, and a right end, said bottom side defining a reference plane; a first plurality of electrically conductive layers embedded within the ceramic chip that form a first capacitor, each of said first plurality of electrically conductive layers extending transversely within the ceramic chip parallel to the reference plane; a second plurality of electrically conductive layers embedded within the ceramic chip that form a second capacitor, each of said second plurality of electrically conductive layers extending transversely within the ceramic chip parallel to the reference plane;
wherein:
the first plurality of electrically conductive layers includes a first set of electrically conductive layers and a second set of electrically conductive layers, said first set of electrically conductive layers being electrically interconnected to form a first electrode of the first capacitor, and said second set of electrically conductive layers being electrically interconnected to form a second electrode of the first capacitor; andthe second plurality of electrically conductive layers includes a third set of electrically conductive layers and a fourth set of electrically conductive layers, said third set of electrically conductive layers being electrically interconnected to form a first electrode of the second capacitor, and said fourth set of electrically conductive layers being electrically interconnected to form a second electrode of the second capacitor;the first capacitor includes at least one electrically conductive layer that is non-coplanar with any other electrically conductive layer of the second capacitor; a plurality of electrically conductive pads on the top side of the ceramic chip, each of the plurality of electrically conductive pads having a flat surface that is parallel to and at a distance away from the top side, and being otherwise configured to function as a wire-bondable capacitor terminal; and a plurality of vias in the ceramic chip, each of the plurality of vias connecting a respective one of the plurality of electrically conductive pads to a respective one of the first and second capacitors;
wherein at least one via does not extend from the top side to the bottom side;wherein at least one of the electrically conductive pads is not connected to any via that extends into the ceramic chip and is disposed proximate one of the plurality of electrically conductive layers embedded within the ceramic chip so as to form an additional capacitor; whereby the multi-layer ceramic capacitor device enables electrical connection of the first and second capacitors to a printed circuit board by wire bonding to the plurality of electrically conductive pads on the top side instead of requiring solder connections to terminals on the left and right ends.