Semiconductor device and driving method of semiconductor device

摘要

To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

主权项

1. A semiconductor device comprising:
a memory element comprising:
a first memory comprising a first data holding portion and a second data holding portion; anda second memory comprising a third data holding portion and a fourth data holding portion, wherein the first data holding portion is electrically connected to a first bit line through a first transistor, wherein the second data holding portion is electrically connected to a first inverted bit line through a second transistor, wherein a first word line is electrically connected to each of a gate of the first transistor and a gate of the second transistor, wherein the third data holding portion is electrically connected to the second data holding portion through a third transistor, wherein the fourth data holding portion is electrically connected to the first data holding portion through a fourth transistor, wherein a second word line is electrically connected to each of a gate of the third transistor and a gate of the fourth transistor, wherein the third data holding portion is electrically connected to one electrode of a first capacitor, wherein the fourth data holding portion is electrically connected to one electrode of a second capacitor, wherein the other electrode of the first capacitor is electrically connected to a first power supply line, wherein the other electrode of the second capacitor is electrically connected to the first power supply line, wherein the third transistor and the fourth transistor are configured to be turned off when data is written to the first data holding portion, wherein the third transistor and the fourth transistor are configured to be turned off just before supply of power to the first memory is stopped, and wherein each of the third transistor and the fourth transistor comprises an oxide semiconductor layer comprising a channel formation region comprising indium.