发明名称 |
Timing scrambling method and timing control circuit thereof |
摘要 |
A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, includes adjusting a selecting signal according to a clock signal; selecting one of a plurality of scrambling generating units according to the selecting signal to generate a timing scrambling signal; and generating scrambling data for the plurality of source driving devices according to the timing scrambling signal. |
申请公布号 |
US9299285(B2) |
申请公布日期 |
2016.03.29 |
申请号 |
US201314010502 |
申请日期 |
2013.08.26 |
申请人 |
NOVATEK Microelectronics Corp. |
发明人 |
Yang Shun-Hsun;Su Chia-Wei |
分类号 |
G09G3/36;G09G3/20 |
主分类号 |
G09G3/36 |
代理机构 |
|
代理人 |
Hsu Winston;Margo Scott |
主权项 |
1. A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, the timing scrambling method comprising:
selecting a first timing scrambling signal of a first scrambling generating unit among a plurality of scrambling generating units in a first period of a clock signal as a scrambling input signal; selecting a second timing scrambling signal of a second scrambling generating unit among the plurality of scrambling generating units in a second period of the clock signal as the scrambling input signal, wherein the second period is subsequent to the first period; and generating scrambling data for the plurality of source driving devices according to the scrambling input signal and source driving data of the corresponding source driving device. |
地址 |
Hsinchu Science Park, Hsin-Chu TW |