发明名称 Serial-parallel interface circuit with nonvolatile memory
摘要 A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines.
申请公布号 US9298653(B2) 申请公布日期 2016.03.29
申请号 US201414166869 申请日期 2014.01.29
申请人 NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY 发明人 Peng Sheng-Yu;Lai Chi-An;Lee Chiang-Hsi;Wang Tzu-Yun
分类号 G06F13/14;G06F13/28;G11C16/04;G11C7/10;G11C5/06 主分类号 G06F13/14
代理机构 CKC & Partners Co., Ltd. 代理人 CKC & Partners Co., Ltd.
主权项 1. A serial-parallel interface circuit comprising: a control module generating a plurality of control signals, the control signals comprising a high voltage control signal and a memory control signal; an input terminal receiving a plurality of digital data from external, the digital data being transmitted to the input terminal in series; and a plurality of memory modules coupled to the input terminal and receiving the control signals from the control module, the input terminal transmitting the digital data to the memory modules, one of the memory modules comprising: a memory unit storing one bit of the digital data or transmitting the one bit of the digital data based on the high voltage control signal and the memory control signal, the memory control signal comprising a high memory control signal and a low memory control signal; anda plurality of output signal lines respectively coupled to the memory modules, the memory unit transmitting the one bit of the digital data to one of the output signal lines.
地址 Taipei TW