Data-aware SRAM systems and methods forming same

摘要

Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

主权项

1. A method of generating an output voltage signal comprising:
receiving a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal; receiving a sleep signal, a selection signal, and a data input signal; generating a first voltage control output signal based on the sleep signal, the selection signal, and the data input signal; generating a second voltage control output signal based on the sleep signal, the selection signal, and the data input signal; generating an output voltage signal, wherein the output voltage signal has a value equal to the first input voltage signal when either the sleep signal is High or when the sleep signal is low, the selection signal is high, and the data input signal is High; and wherein the output voltage signal has a value equal to the second input voltage signal when either the sleep signal is low and the selection signal is low or when the sleep signal is low, the selection signal is high, and the data input signal is low.