Data synchronization circuit

摘要

The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

主权项

1. A circuit comprising:
a first circuit block adapted to receive a first clock signal and to provide a first output data signal at a first time determined by the first clock signal; a second circuit block adapted to receive a second clock signal and to provide a second output data signal at a second time determined by the second clock signal; a clock bus coupled to an output of the first circuit block and also to an output of the second circuit block, the output of the first circuit block being different from the output of the second circuit block, a third clock signal generated on the clock bus based on a first edge of the first clock signal and a second edge of the second clock signal; and a synchronization unit coupled to the clock bus and adapted to sample the first and second output data signals based on the third clock signal.