发明名称 SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM
摘要 A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.
申请公布号 US2016088246(A1) 申请公布日期 2016.03.24
申请号 US201514949411 申请日期 2015.11.23
申请人 Sony Corporation 发明人 Tanaka Kenichi
分类号 H04N5/369;H04N5/225;H04N5/374;H04N5/378;H04N5/3745 主分类号 H04N5/369
代理机构 代理人
主权项 1. An imaging device comprising: a pixel circuit; and a pixel signal readout circuit including a comparator, the comparator comprising: a first circuit including a first transistor that receives a pixel signal from the pixel circuit, a second transistor that receives a reference signal, and a third transistor, one of a source and a drain of the third transistor being coupled to the first transistor and the second transistor, and the other of the source and the drain of the third transistor being coupled to a first fixed voltage line; anda second circuit including a fourth transistor coupled to the first circuit and a second fixed voltage line, a fifth transistor coupled to the fourth transistor in series and the first fixed voltage line, a sixth transistor coupled to a gate of the fifth transistor and a drain or a source of the fifth transistor, a seventh transistor coupled to the second fixed voltage line, and an eighth transistor coupled to the seventh transistor and the first fixed voltage line.
地址 Tokyo JP