| 摘要 |
A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal. |
| 主权项 |
1. A PLL-VCO based integrated circuit aging monitor, comprising:
a) a control circuit; b) a monitoring circuit, the monitoring circuit comprising: a reference circuit, an aging generation circuit and a comparison circuit, wherein, the reference circuit is a phase locking loop (PLL) circuit which is insensitive to a parameter error caused by aging of a circuit; the aging generation circuit is a voltage controlled oscillator (VCO) circuit which is sensitive to the parameter error caused by the aging of the circuit; and c) an output circuit;wherein
the control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit; an output end of the PLL circuit is connected to a first input end of the comparison circuit, and an output end of the VCO circuit is connected to a second input end of the comparison circuit, and an output end of the comparison circuit is connected to an input end of the output circuit; an input end of the PLL circuit inputs a reference clock signal; the output end of the PLL circuit outputs a reference frequency signal, and the output end of the VCO circuit outputs a monitoring frequency signal; and when in use, the comparison circuit compares the reference frequency signal with the monitoring frequency signal to yield aging data and then outputs the aging data via an output end of the output circuit; an amplitude of the reference clock signal is the same as that of a clock frequency signal output by the VCO circuit in an initial state; a period of the clock frequency signal output by the VCO circuit in the initial state is denoted as T, and the period of the reference clock signal is T1, and T≦T1≦2T. |
