3D MEMORY HAVING NAND STRINGS SWITCHED BY TRANSISTORS WITH ELONGATED POLYSILICON GATES

摘要

A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.

主权项

1. A 3D nonvolatile memory, comprising:
a semiconductor substrate; a 3D array of memory cells arranged in a three-dimensional pattern on top of said semiconductor substrate; said 3D array of memory cells being organized into a 2D array of NAND strings aligned vertically relative to the substrate, each NAND string further comprising:
a daisy-chain of vertically stacked memory cells;a channel having first and second ends terminated by a source-side transistor on the first end and a drain-side transistor on the second end; andsaid source-side transistor having a source-side control gate, which comprises a source-side doped polysilicon gate elongated in a direction parallel to said channel; and a source-side metal gate strapped in a direction perpendicular to said channel to the source-side doped polysilicon gate.