FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR

摘要

Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.

主权项

1. A method for assembling a Fan-Out Wafer Level Package (FO-WLP), comprising:
dispensing a mold material over a first temporary substrate; positioning a first microelectronic component carried by a the first temporary substrate in back-to-back relationship with a second microelectronic component carried by a second temporary substrate; overmolding the first and second microelectronic components while positioned in the back-to-back relationship to produce a double-sided molded package body; removing the first temporary substrate to expose a first principal surface of the double-sided molded package body at which the first microelectronic component is exposed; removing the second temporary substrate to expose a second, opposing principal surface of the double-sided molded package body at which the second microelectronic component is exposed; forming one or more Redistribution Layers (RDLs) over the first principal surface of the molded package body after removal of the first temporary substrate and prior to removal of the second temporary substrate; and bonding at least one externally-mounted microelectronic device to the one or more RDLs over the first principal surface.