| 摘要 |
In the present invention, a memory diagnosis circuit is provided with the following: an error detection and correction circuit (3) that performs error detection of N (N is a natural number of 2 or greater) bits or more and error correction of (N-1) bits or less for data which is read from a memory (2, 11); a first data buffer (5) in which is held the data that was error corrected by the error detection and correction circuit; a second data buffer (6) in which the data is directly held; a comparator (7) that compares the data values held in the first and second data buffers; and an error detection and correction monitoring circuit (8, 9). In the error detection and correction monitoring circuit, on the basis of the comparison results of the comparator, the data value held in the first data buffer is validated. Or, in the error detection and correction monitoring circuit, the data value held in the first data buffer is invalidated, and an abnormal signal is output. |
