| 摘要 |
PURPOSE:To delete an old data reading time at the time of whole byte writing and to shorten a memory cycle by reading the old data from a memory only at the time of partial writing. CONSTITUTION:A memory control circuit 6 identifies whether a whole byte writing or a partial writing is obtained. As a result, at the time of whole byte writing, the memory control circuit 6 commands to a response generating circuit 7 and generates a response signal. A CPU 1, when the response signal is received, supplies the writing data to an ECC circuit 5. The ECC circuit 5 prepares an error correction code W with the writing data an new data. When a writing timing signal is generated from the control circuit 6, a memory 4 writes the new data and the error correction code W into the said address. At the time of partial writing, the address of the old data for the memory 4 is designated and the reading is commanded. |
